Re: FW: Technologically Challenged

From: Stephen J. Rock (
Date: Mon Mar 30 1998 - 17:27:59 EEST

wayne l foss wrote:
> Have you ever tried to explain rapid prototyping concepts to a
> electrical engineer?

Hmmm... Any implication here, Wayne... ?

As a fellow spark jockey, I have to point out that much of the
Electrical Engineering world was quite proficient at grasping the
concepts of layer-wise additive fabrication (VLSI chips) long
before mechanical Rapid Prototyping relying on layer-wise additive
fabrication was ever brought to market.

More generally, there are also some interesting parallels between
the time-to-market reducing goals of mechanical RP and work
I was involved with in the early 90's and would classify as
electrical RP. Field Programmable Gate Arrays allow EE designs
normally targeted for VLSI fab to be "downloaded" to a chip
(or hypercube topology of many such programmable chips) and
tested -- often at a speed somewhat reduced from that attainable
on a piece of dedicated silicon. More recent developments
have provided paths for these designs to be migrated to less
expensive and non-reprogrammable silicon in limited quantities
(relative to typical VLSI quantities) in much the way
Rapid Tooling developments have extended the utility of what
began as one-of Rapid Prototyping.

Those interested can learn more at:

Stephen J. Rock
NYS Center for Advanced Technology
in Automation, Robotics & Manufacturing
Rensselaer Polytechnic Institute
Troy, NY 12180  USA
(518)276-8652  Fax -4897

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